In a current-output type digital-to-analog conversion circuit, resistors weighted in accordance with bits are connected in parallel via switches. When a certain voltage is applied to the resistors, the total sum of currents flowing through the resistors turned on by the switches is a total current amount, and a current corresponding to an input digital value is output.
FIG. 1 depicts a digital-to-analog converter (hereinafter referred to as a “DA converter”) 100 as a semiconductor integrated circuit. The DA converter depicted in FIG. 1 is referred to as a conventional scheme 1. A current generated by a current source 122 is supplied via a p-channel metal-oxide-semiconductor (PMOS) transistor P1 to a current cell array 124. The drains of PMOS transistors Pa of the current cell array 124 are connected to the corresponding differential switches of a switch group 126. Each differential switch is made up of a pair of PMOS transistors Qxi and Qyi. Decode signals SiPx and SiPy obtained by decoding an input digital signal of N bits are applied to the pair of PMOS transistors Qxi and Qyi of the differential switch corresponding to the decode signals SiPx and SiPy. Through the decode signals SiPx and SiPy, the differential switch is controlled so as to be turned on or off. In addition, i is 0, 1 to n in FIG. 1.
The drain of the PMOS transistor Qxi is connected to a current path xi. The drain of the PMOS transistor Qyi is connected to a current path yi. Either the current path xi or the current path yi is selected depending on whether the differential switch is in the ON state or in the OFF state, and current values for differential switches are added together. Output currents Ix and Iy from the switch group 126 flow through the current paths xi and yi, respectively. The output currents Ix and Iy are converted into a voltage by a current-to-voltage conversion circuit 128, and the voltage passes through a buffer circuit 130 and is output as an analog signal from an output terminal 132.
In the configuration of FIG. 1, voltage drops occur between the sources and drains of the PMOS transistors Qxi and Qyi of the differential switch. Moreover, currents Ia0 to Ian flowing through transistors of the current cell array 124 easily vary under the influence of the Early effect. This is because variations in drain voltages Vds of the MOS transistors Pa directly influence the currents Ia0 to Ian.
To reduce current errors due to variations in the drain voltages Vds of the MOS transistors Pa, it is conceivable to replace the current cell array 124 with cascade current mirrors. In this case, as depicted in FIG. 2, voltage drops across MOS transistors become larger.
FIG. 2 depicts a configuration in which currents i3 and i4 generated in a cascade current mirror circuit 210 are connected to differential switches SW1 and SW2, respectively. The DA converter depicted in FIG. 2 is referred to as a conventional scheme 2. The differential switch SW1 is made up of a pair of transistors Q1 and Q2. An input digital signal PD1 and its inverse are applied to the gates of the transistors Q1 and Q2, respectively. The differential switch SW2 is made up of a pair of transistors Q3 and Q4. An input digital signal PD2 and its inverse are applied to the gates of the transistors Q3 and Q4, respectively. In a steady current source 215, the gate potential of a transistor T3 is determined by a transistor T1, so that the drain potential of a transistor T2 is fixed. The gate potential of the transistor T2 is applied to the gates of transistors T4 and T6, so that a current i2 is copied. The drain potential of the transistor T4 is fixed by a transistor T5, and the drain potential of the transistor T6 is fixed by a transistor T7. In this way, degradation of current accuracy due to the Early effect is reduced.
With the configuration of FIG. 2, however, voltage drops between the drains and the sources of the transistors Q1 to Q4 used for the differential switches SW1 and SW2 not only occur but also increase by amounts corresponding to the transistors T5 and T7 added to the cascade current mirror circuit 210.
Another configuration using a current mirror circuit for use in a circuit in which power down operation is performed is known. FIG. 3 depicts an example of a configuration of a current mirror circuit 300 using analog switches. The DA converter depicted in FIG. 3 is referred to as a conventional scheme 3. In the current mirror circuit 300, pairs of switches (31, 41), (32, 42), (33, 43), and (34, 44) are arranged for transistors Tr2, Tr3, Tr4, and Tr5, respectively. Each switch is controlled by input data bits so as to be turned on or off, thereby connecting the gate of the corresponding transistor Tr2, Tr3, Tr4, or Tr5 either to a VDD line or to the drain of a transistor Tr1. The transistors Tr2 to Tr5 are formed to have different sizes, and copy a reference current Iref in accordance with their sizes such that the reference current Iref is increased by a factor of 2n-1. With the configuration of FIG. 3, voltage drops across the switches 41, 42, 43, and 44 directly influence currents flowing through the transistors Tr2 to Tr5, and therefore the mirror ratio accuracy is degraded.
Japanese Laid-open Patent Publication Nos. 2010-35090 and 2006-313568 are examples of the related art.